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1 publication date: march 2004 sdb00102aeb data sheet semiconductor company matsushita electric industrial co., ltd. AN15865A part no. package code no. *qfh080-p-1420h
AN15865A 2 sdb00102aeb contents ? overview ?????????????????????????????????????????. 3 ? features ?????????????????????????????????????????.. 3 ? applications ???????????????????????????????????????? 3 ? package ?????????????????????????????????????????. 3 ? type ?????????????...?????????????????????????????. 3 ? application circuit example ?????????????????????????????????. 4 ? block diagram ??????...????????????????????????????????. 5 ? pin descriptions ??????????????????????????????????????. 7 ? absolute maximum ratings ?????????????????????????????????. 10 ? operating supply voltage range ?????..?????????????????????????. 10 ? electrical characteristics ??????????????????????????????????. 11 ? i 2 c bus conditions ????????????????????????????????????. 15 ? test circuit diagram ????????????????????????????????????. 26 ? technical data ??????????????????????????????????????. 27 1. circuit diagrams of the input/output par t and pin function descriptions ??????????????. 27 2. notes on video gain????????????????????????????????????. 35 3. other supplementary matters??????????????.?????????????????? 35 ? usage notes ???????????????.????????????????????????. 36
AN15865A 3 sdb00102aeb output h2/v2 *2 g(y1-6)(cv1-7)/b(u1-6)(sy4-7)/ r(v1-6)(sc4-7) out5 h1/v1 *1 g(y1-6)(cv1-7)/b(u1-6)(sy4-7)/ r(v1-6)(sc4-7) out4 cv1-7(sy4-7)/ sc4-7 out3 cv1-7(sy4-7)/ sc4-7 out2 cv1-7/sy4-7/ sc4-7 out1 AN15865A the video switch ic including the synchronous separation function for tv ? overview the AN15865A has the video switch portion which consists of a five-channel output in a ten-channel input, the synchronous separation function, the afc function, and the format detection function. it contributes to the rationalization design of a tel evision system. ? features 1. support multi scan / auto format identification 480i, 576i, 480p, 576p, 720p, 1080i, 1152i, 1152i/letter (both 50 hz & 60 hz) 2. field 1 or 2 monitor out is available 3. auto distinction in the selected input (sync on cv/y or sync on sy or no input signal) 4. dummy sync output 480i, 576i, 480p, 576p, 720p, 1080i (both 50 hz & 60 hz) 5. sync separation with afc w/o external x-tal or clock 6. 2 values, 3 values sync identification 7. rgb yuv converter (ccir standard, bta standard, gbr matrix) 8. each output can be switched between lpf (6 mhz) & through 9. each output can be switched among 0 db, 6 db or mute 10. macrovision 11. comparators for pin detection 4 (connected / open) 12. comparators for aspect ratio 4 (4:3 video / 4:3 letter box / 16:9 video) 13. high frequency (0 db at 50 mhz) 14. support the i 2 c bus 15. various input mode can be selected by using flexible internal switch ? applications y ic for color tv ? package y 80 pin plastic high profile quad flat package (qfp type) ? type y silicon monolithic bicmos ic input h1/v1 y1(g1)/u1(b1)/v1(r1) in10 h2/v2 y2(g2)/u2(b2)/v2(r2) in9 h3/v3 y3(g3)/u3(b3)/v3(r3) in8 h4/v4 y4/u4/v4 cv7/sy7/sc7 in7 h5/v5 y5/u5/v5 cv6/sy6/sc6 in6 h6/v6 y6/u6/v6 cv5/sy5/sc5 in5 y7/u7/v7 cv4/sy4/sc4 in4 cv3 in3 cv2 in2 cv1 in1 note) *1: independent hv only *2: independent hv or sync-separated hv
AN15865A 4 sdb00102aeb ? application circuit example note : v cc1 , v cc2 = 9 v 0.5 v v cc3 , v cc4 = 5 v 0.3 v slvadr : 5 v( 8chex / 8dhex ) 0 v( 84hex / 85hex ) output 2 output 4 3.3 v input 4 input 5 input 10 output 5 input 7 input 8 input 1 input 2 input 6 input 9 input 6 input 9 0.01 f output 3 output 1 vin6 v6/sc5 hin6 u6/sy5 sb5 y6/cv5 sa5 cv1 gnd1 cv2 sa3 sb3 cv3 u7/sy4 sa4 y7/cv4 sb4 v7/sc4 sa6 y5/cv6 sb6 u5/sy6 v5/sc6 hin5 sy1 dcout sc1 cv2/sy2 gnd sc2 gnd2 slvadr v cc3 g1/y1 sc3 cv3/sy3 gnd v cc2 cv1 hout1 vin5 y4/cv7 hin4 u4/sy7 vin4 v cc1 v4/sc7 hin3 b3/u3 vin3 r3/v3 v cc4 hin2 g2/y2 g3/y3 b2/u2 hin1 b1/u1 vin1 afc1 r1/v1 sync-out gnd4 g1/y1 sync-in r2/v2 sda scl field monitor r2/v2 vout2 hout2 b2/u2 gnd3 g2/y2 vsyncsepa r1/v1 vout1 b1/u1 vin2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 input 3 9 v 5 v 10 k ? 9 v 5 v 0.47 f 4.7 f 4.7 k ? 75 k ? 0.022 f
AN15865A 5 sdb00102aeb switch v mask pulse h switch 2 ( afc-v or independent v ) ( afc-h or independent h ) hvco h counter v counter phase detector independent v (selected) independent h (selected) h sync separation v sync separation auto sync distinction sync status detector ( 2 or 3 ) macro vision system mode control automatic polarity control h 2 automatic polarity control v 2 afc filter v switch 1 lock det field monitor sync-out v sync sepa h switch 1 ( independent v ) ( independent h ) automatic polarity control v 1 automatic polarity control h 1 vin1 vin2 vin6 hin1 hin2 hin6 cv1 cv2 cv3 y7/cv4 sy4 y6/cv5 sy5 y5/cv6 sy6 y4/cv7 sy7 y3 y2 y1 v switch 2 system status check clamp sync-in vout1 hout1 vout2 hout2 ? block diagram (sync separation and afc system)
AN15865A 6 sdb00102aeb ? block diagram (continued) (video-switch) in6 in7 in5 in4 cv1 cv2 cv3 y7/cv4 u7/sy4 v7/sc4 y4/cv7 u4/sy7 v4/sc7 hin4 vin4 y5/cv6 u5/sy6 v5/sc6 hin5 vin5 y6/cv5 u6/sy5 v6/sc5 hin6 vin6 sync-sep sync-sep g3/y3 b3/u3 r3/v3 in8 g2/y2 hin3 vin3 sb6 g1/y1 b1/u1 r1/v1 hin1 vin1 b2/u2 r2/v2 hin2 vin2 sa4 sa5 sa6 sa3 sb4 sb5 sb3 hout1 vref sync-sep vout1 switch afc hout2 vout2 in9 in10 out1 cv1 sy1 sc1 out2 out3 switch through sc3 6/0 db 6/0 db lpf 6/0 db sc2 6/0 db 6/0 db 6/0 db cv3/sy3 lpf lpf cv2/sy2 lpf 6/0 db 6/0 db 6/0 db lpf lpf lpf g2/y2 b2/u2 r2/v2 lpf 6/0 db lpf 6/0 db lpf 6/0 db out4 g1/y1 b1/u1 r1/v1 lpf 6/0 db lpf 6/0 db lpf 6/0 db out5 ccir bta gbr matrix 2 matrix 3 ccir bta gbr matrix 2 matrix 3 in1 in2 in3 + + +
AN15865A 7 sdb00102aeb ? pin descriptions description type pin name pin no. sets the i 2 c bus slave address in slvadr 35 cv2/sy2 signal output out cv2/sy2 34 ground ground gnd2 31 cv3/sy3 signal output out cv3/sy3 30 ground ground gnd 29 b1/u1 signal output out b1/u1 24 independent v signal output 1 out vout1 23 r1/v1 signal output out r1/v1 22 ground ground gnd3 21 g2/y2 signal output out g2/y2 20 independent h signal output 2 out hout2 19 b2/u2 signal output out b2/u2 18 independent v signal output 2 out vout2 17 ground ground gnd 33 sc2 signal output out sc2 32 sc3 signal output out sc3 28 5.0 v power supply power supply v cc3 27 g1/y1 signal output out g1/y1 26 independent h signal output 1 out hout1 25 r2/v2 signal output out r2/v2 16 field change signal output out field monitor 15 v sync separation filter in / out v sync sepa 14 sync signal input for sync separation in sync-in 13 sync signal output for sync separation out sync-out 12 ground ground gnd4 11 afc filter in / out afc1 10 r1/v1 signal input in r1/v1 9 independent v signal input 1 in vin1 8 b1/u1 signal input in b1/u1 7 independent h signal input 1 in hin1 6 g1/y1 signal input in g1/y1 5 i 2 c bus clock input in scl 4 i 2 c bus data input in / out sda 3 r2/v2 signal input in r2/v2 2 independent v signal input 2 in vin2 1
AN15865A 8 sdb00102aeb ? pin descriptions (continued) y4/cv7 signal input in y4/cv7 66 independent v signal input 5 in vin5 65 u4/sy7 signal input in u4/sy7 68 independent h signal input 4 in hin4 67 cv4 signal input in y7/cv4 54 pin status detection for input channel 3 in sb3 53 cv3 signal input in cv3 52 aspect ratio detection for input channel 3 in sa3 51 cv2 signal input in cv2 50 ground ground gnd1 49 cv1 signal input in cv1 48 aspect ratio detection for input channel 5 in sa5 47 y6/cv5 signal input in y6/cv5 46 pin status detection for input channel 5 in sb5 45 description type pin name pin no. v4/sc7 signal input in v4/sc7 70 independent v signal input 4 in vin4 69 v5/sc6 signal input in v5/sc6 64 independent h signal input 5 in hin5 63 u5/sy6 signal input in u5/sy6 62 pin status detection for input channel 6 in sb6 61 y5/cv6 signal input in y5/cv6 60 aspect ratio detection for input channel 6 in sa6 59 sc4 signal input in v7/sc4 58 pin status detection for input channel 4 in sb4 57 sy4 signal input in u7/sy4 56 aspect ratio detection for input channel 4 in sa4 55 u6/sy5 signal input in u6/sy5 44 independent h signal input 6 in hin6 43 v6/sc5 signal input in v6/sc5 42 independent v signal input 6 in vin6 41 cv1 signal output out cv1 40 9.0 v power supply power supply v cc2 39 sy1 signal output out sy1 38 output dc voltage corresponding to s2 out dcout 37 sc1 signal output out sc1 36
AN15865A 9 sdb00102aeb ? pin descriptions (continued) b2/u2 signal input in b2/u2 80 description type pin name pin no. independent h signal input 2 in hin2 79 g2/y2 signal input in g2/y2 78 5.0 v power supply power supply v cc4 77 r3/v3 signal input in r3/v3 76 independent v signal input 3 in vin3 75 b3/u3 signal input in b3/u3 74 independent h signal input 3 in hin3 73 g3/y3 signal input in g3/y3 72 9.0 v power supply power supply v cc1 71
AN15865A 10 sdb00102aeb ? absolute maximum ratings ? operating supply voltage range 23 i cc3 , i cc4 note unit rating symbol parameter a no. ma 130 i cc1 , i cc2 supply current 2 5.5 v cc3 , v cc4 *3 c ? 55 to + 125 t stg storage temperature 5 *3 c ? 20 to +75 t opr operating ambient temperature 4 *2 mw 773 p d power dissipation 3 *1 v 10.0 v cc1 , v cc2 supply voltage 1 note) *1: the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: the power dissipation shown is the value at t a = 75 c for the independent ic package without a heat sink. refer to the package power dissipation prepared else and use under the condition not exceeding the allowable value. *3: except for the operating ambient temperature and storage temperature, all ratings are for t a = 25 c. note unit range symbol parameter * 4.7 to 5.3 v cc3 , v cc4 ? v 8.5 to 9.5 v cc1 , v cc2 operating supply voltage range note) *: the values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
AN15865A 11 sdb00102aeb ? electrical characteristics at v cc1 , v cc2 = 9 v, v cc3 , v cc4 = 5 v note) t a = 25 c 2 c unless otherwise specified. 1 1 1 1 1 1 1 1 1 1 1 1 test circuits 1 1 1 1 1 1 1 1 1 1 [hout items] db 6.2 5.7 5.2 g v6 khz 15.84 15.75 15.65 mode 480i fh free5 hout2 free-run freq.5 21 khz 37.72 37.50 37.28 mode 720p/50 fh free4 hout2 free-run freq.4 20 mode 1080i/50 mode 576i mode 1080i, 720p, 1152i, 1152i /letter mode 480i, 576i db 0 ?3 ?6 1.0 v[p-p] input at 6 mhz/500 khz (lpf on) f lpf1 lpf characteristic1 measure the difference from the output dc level while in mute mode. 1.0 v[p-p] input at 5 mhz between contiguity channels 1.0 v[p-p] input at 30 mhz/500 khz (during 6 db output)(lpf off) no signal input v cc3 , v cc4 hz ?700 ? ? fh pulllow h pull in range lower 16 khz 15.72 15.62 15.53 fh free1 hout2 free-run freq.1 17 mode 480p, 576p v ? 3.3 h hi hout1/2 high level 2.8 v 0.4 ? dvd o output dc level ? 0.4 ma 20 15 i cq34 quiescent current 10 8 v 0.5 ? ? h lo hout1/2 low level 11 s 2.0 1.6 1.2 h wid1 hout2 pulse width(1) 12 s 1.4 1.0 0.6 h wid2 hout2 pulse width(2) 13 ns 800 660 520 h wid3 hout2 pulse width(3) 14 hz ? ? 700 fh pullup h pull in range upper 15 khz 31.43 31.25 31.06 mode 576p, 1152i, 1152i/letter fh free2 hout2 free-run freq.2 18 khz 28.34 28.17 28.00 fh free3 hout2 free-run freq.3 19 ma 127 118 109 no signal input v cc1 , v cc2 i cq12 quiescent current 1 2 db 0.3 ?0.2 ?0.7 f = 500 khz, v in = 1 v[p-p] (except composite pass) g v0 video gain 3 db 1.0 ? ?1.5 f v1 video frequency response 1 4 db 1.0 ? ?1.5 1.0 v[p-p] input at 30 mhz/500 khz (during 0 db output) (composite in) f v2 video frequency response 2 5 db ?50 ? ? ct v crosstalk 6 7 db ?25 ? ? 1.0 v[p-p] input at 10 mhz/500 khz (lpf on) f lpf2 lpf characteristic2 9 10 limits typ unit max conditions note min symbol parameter b no.
AN15865A 12 sdb00102aeb ? electrical characteristics (continued) at v cc1 , v cc2 = 9 v, v cc3 , v cc4 = 5 v note) t a = 25 c 2 c unless otherwise specified. [dcout] v 0.5 ? ? 1 v dcl s2 compatible dc level l [00] 35 v 2.8 ? 1.4 1 v dcm s2 compatible dc level m [01] 36 v ? ? 4.0 1 v dch s2 compatible dc level h [11] 37 [address pins] v 1.5 ? ? 1 v adr1 address setting voltage (84/85hex) 33 v ? ? 2.5 1 v adr2 address setting voltage (8c/8dhex) 34 v ? 3.3 2.8 1 v hi vout1/2 high level 25 v 0.5 ? ? 1 v lo vout1/2 low level 26 h ? 6 ? afc/free mode 480i, 480p, 1080i/60 1 v wid1 vout2 pulse width(1) 27 h ? 6 ? afc/free mode 576p, 1080i/50 1 v wid2 vout2 pulse width(2) 28 h ? 6 ? afc/free mode 1152i/letter 1 v wid3 vout2 pulse width(3) 29 h ? 5 ? afc/free mode 720p/60 1 v wid4 vout2 pulse width(4) 30 h ? 5 ? afc/free mode 576i, 720p/50 1 v wid5 vout2 pulse width(5) 31 h ? 6 ? afc/free mode 1152i 1 v wid6 vout2 pulse width(6) 32 [vout items] khz 45.38 45.11 44.84 mode 720p/60 1 fh free8 hout2 free-run freq.8 24 khz 33.90 33.71 33.51 mode 1 080i/60 1 fh free7 hout2 free-run freq.7 23 1 test circuits khz 31.60 31.41 31.23 mode 480p fh free6 hout2 free-run freq.6 22 limits typ unit max conditions note min symbol parameter b no.
AN15865A 13 sdb00102aeb ? electrical characteristics (continued) at v cc1 , v cc2 = 9 v, v cc3 , v cc4 = 5 v note) t a = 25 c 2 c unless otherwise specified. kbit/s ? ? 100 1 f imax max. frequency allowable to input 41 v 0.4 ? ? the pin voltage with pin 3 suction current set to 3 ma during ack. 1 v ack suction current during ack 38 v 5.5 ? 3.0 1 v ihi scl, sda signal input high level 39 v 1.5 ? 0 1 v ilo scl, sda signal input low level 40 [i 2 c interface] test circuits limits typ unit max conditions note min symbol parameter b no. note) the above characteristics are reference values on ic designing and not guaranteed by shipping inspection. start condition slave address ack sub address ack data byte ack stop condition sda t buf t su.sta t hd.sta t su.dat t hd.dat t lo t su.sto scl t r t f t hi t lo
AN15865A 14 sdb00102aeb ? electrical characteristics (reference values for design) at v cc1 , v cc2 = 9 v, v cc3 , v cc4 = 5 v note) t a = 25 c 2 c unless otherwise specified. *1 v ? ? 2.5 1 v sh vin h 57 *1 v 1.5 ? ? 1 v sl vin l 56 *1 v ? ? 2.5 1 h sh hin h 55 *1 v 1.5 ? ? 1 h sl hin l 54 [others] *1 v[p-p] ? ? 2.4 1 v dyv input dynamic range 42 *1 v ? 3.2 ? 1.0 v[p-p] input 0 db mode 1 v sync output sync level 45 *1 v ? 3.5 ? 1 v m mute dc level 43 *1 v ? 3.5 ? 1.0 v[p-p] input 0 db mode 1 v ped output pedestal level 44 [sa sb pins] [vout items] [hout items] *1 hz ? 50 ? mode (v : 50 hz) 1 fv free1 vout2 free-run freq.1 47 *1 hz ? 60 ? mode (v : 60 hz) 1 fv free2 vout2 free-run freq.2 48 *1 v 1.0 ? ? 1 v sal scart ident sa l 49 *1 v 3.0 ? 1.7 1 v sam scart ident sa m 50 *1 v ? ? 4.0 1 v sah scart ident sa h 51 *1 v 1.5 ? ? 1 v sbl pin detect sb l 52 *1 v ? ? 2.5 1 v sbh pin detect sb h 53 1 test circuits *1 khz/ mv ? ?1.4 ? conversion by 6 mhz b h h vco osc. chara. 46 reference values typ unit max conditions note min symbol parameter b no. note) *1 : the characteristics listed above are logical values derived from the design, and as such, all of these cannot be guarant eed. if, in the unlikely case that problems do occur related to these parameters, panasonic will negotiate in good faith with the customer on these matt ers.
AN15865A 15 sdb00102aeb ? i 2 c bus conditions 0 d1 r/w d0 0 d4 1/0 d3 1 d2 0 0 1 84/8c 85/8d d6 d5 d7 sub address note) the change of d3 data is performed by control of a slvadr terminal control register continue as data (x + 1) data (x + 2) as data (x) as as sub address (x) slave address (84 or 8c) s note) as = ack from slave 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 00 : through 01 : ccir standard 10 : bta standard 11 : gbr matrix 00 : through 01 : ccir standard 10 : bta standard 11 : gbr matrix 00 : auto distinction 01 : sync on cv/y use 10 : sync on sy use 11 : free-run out4 signal select out3 signal select 01 out5 signal select out5 sync 0 : afc 1 : independent free-run priority 0 : fixing 1 : auto distinction use out5 sync distinction 02 hvout2 polarity 0 : positive 1 : negative dummy sync mode control (when 02/d7, d6 = '11') out5 matrix out4 matrix 03 out5 gain 0 : 0 db 1 : 6 db out4 gain 0 : 0 db 1 : 6 db sy3/sc3 gain 0 : 0 db 1 : 6 db cv3 gain 0 : 0 db 1 : 6 db sy2/sc2 gain 0 : 0 db 1 : 6 db cv2 gain 0 : 0 db 1 : 6 db sy1/sc1 gain 0 : 0 db 1 : 6 db cv1 gain 0 : 0 db 1 : 6 db 04 field monitor sel 0 : f1 / f2 out 1 : clock moni out 00 : 0 v 01 : 1.9 v 10 : indefinite 11 : 4.5 v out1 dcout out5 lpf 0 : through 1 : lpf on out4 lpf 0 : through 1 : lpf on out3 lpf 0 : through 1 : lpf on out2 lpf 0 : through 1 : lpf on out1 lpf 0 : through 1 : lpf on 05 australia free-run 0 : except australia 1 : australia mode input10 br/uv sel 0 : br select 1 : uv select input9 br/uv sel 0 : br select 1 : uv select input8 br/uv sel 0 : br select 1 : uv select input7 u/sy sel 0 : sy select 1 : u select input6 u/sy sel 0 : sy select 1 : u select input5 u/sy sel 0 : sy select 1 : u select input4 u/sy sel 0 : sy select 1 : u select 06 test70 test71 test72 test73 test74 test75 test76 test77 07 test80 test81 test82 test83 test84 test85 test86 test87 08 out2 signal select out1signal select 00 d1 d0 d4 d3 d2 d6 d5 d7 sub address note) please send data "00" to sub-address "07" and "08". r/w = 0 y the AN15865A in i 2 c bus control performs switch mode selection, matrix se lection, gain selection, lpf selection, synchronous mode selection and freerun mode selection through a control regist er and detects the system status, aspect and pin information through a status register. the upper seven address bits are allocated to the slave address while the lsb is allocated to the r/w bit. the r/w bit corresponds to the control register with with the bi t set to 0 and corresponds to the status register with the bit set to 1. y the AN15865A selects slave address 84 or 8c(hex) according to the status of the slvadr pin. address 84(hex) will be selected with the slvadr pin grounded the the gnd side. address 8c(hex) will be selected with the pin grounded to the 5-v line.
AN15865A 16 sdb00102aeb ? i 2 c bus conditions (continued) out1 signal select dc dc dc 0 1 1 1 dc dc dc 0 0 1 1 sc7 in7 sy7 in7 sy7 + sc7 in7 in7 0 1 0 1 sc7 in7 sy7 in7 cv7 in7 1 0 0 1 sc6 in6 sy6 in6 sy6 + sc6 in6 in6 0 0 0 1 dc dc dc 1 1 0 1 dc dc dc 1 0 1 1 sc4 in4 sy4 in4 cv4 in4 1 1 0 0 dc dc cv3 in3 0 1 0 0 sc5 in5 sy5 in5 cv5 in5 1 0 1 0 sc4 in4 sy4 in4 sy4 + sc4 in4 in4 0 0 1 0 dc dc cv1 in1 0 0 0 0 dc dc cv2 in2 1 0 0 0 sc5 in5 sy5 in5 sy5 + sc5 in5 in5 0 1 1 0 sc6 in6 sy6 in6 cv6 in6 1 1 1 0 dc *1 dc dc 1 1 1 1 cv1 out1 sy1 out1 sc1 out1 00/d5 00/d4 00/d6 00/d7
AN15865A 17 sdb00102aeb ? i 2 c bus conditions (continued) out2 signal select sc7 in7 sy7 + sc7 in7 in7 0 1 1 1 sc7 in7 cv7 in7 0 0 1 1 sc6 in6 sy6 in6 0 1 0 1 sc6 in6 cv6 in6 1 0 0 1 sc5 in5 sy5 + sc5 in5 in5 0 0 0 1 sc6 in6 sy6 + sc6 in6 in6 1 1 0 1 sc7 in7 sy7 in7 1 0 1 1 sc4 in4 cv4 in4 1 1 0 0 dc cv3 in3 0 1 0 0 sc4 in4 sy4 + sc4 in4 in4 1 0 1 0 sc4 in4 sy4 in4 0 0 1 0 dc cv1 in1 0 0 0 0 dc cv2 in2 1 0 0 0 sc5 in5 cv5 in5 0 1 1 0 sc5 in5 sy5 in5 1 1 1 0 dc *1 dc 1 1 1 1 cv2/sy2 out2 sc2 out2 00/d1 00/d0 00/d2 00/d3
AN15865A 18 sdb00102aeb ? i 2 c bus conditions (continued) out3 signal select sc7 in7 sy7 + sc7 in7 in7 0 1 1 1 sc7 in7 cv7 in7 0 0 1 1 sc6 in6 sy6 in6 0 1 0 1 sc6 in6 cv6 in6 1 0 0 1 sc5 in5 sy5 + sc5 in5 in5 0 0 0 1 sc6 in6 sy6 + sc6 in6 in6 1 1 0 1 sc7 in7 sy7 in7 1 0 1 1 sc4 in4 cv4 in4 1 1 0 0 dc cv3 in3 0 1 0 0 sc4 in4 sy4 + sc4 in4 in4 1 0 1 0 sc4 in4 sy4 in4 0 0 1 0 dc cv1 in1 0 0 0 0 dc cv2 in2 1 0 0 0 sc5 in5 cv5 in5 0 1 1 0 sc5 in5 sy5 in5 1 1 1 0 dc *1 dc 1 1 1 1 cv3/sy3 out3 sc3 out 01/d5 01/d4 01/d6 01/d7
AN15865A 19 sdb00102aeb ? i 2 c bus conditions (continued) out4 signal select indefinite indefinite dc dc cv1 in1 0 0 0 0 indefinite indefinite dc dc cv2 in2 1 0 0 0 indefinite indefinite dc dc cv3 in3 0 1 0 0 indefinite indefinite v7/sc4 in4 u7/sy4 in4 y7/cv4 in4 1 1 0 0 vin6 in5 hin6 in5 v6/sc5 in5 u6/sy5 in5 y6/cv5 in5 0 0 1 0 vin5 in6 hin5 in6 v5/sc6 in6 u5/sy6 in6 y5/cv6 in6 1 0 1 0 vin4 in7 hin4 in7 v4/sc7 in7 u4/sy7 in7 y4/cv7 in7 0 1 1 0 vin3 in8 hin3 in8 r3/v3 in8 b3/u3 in8 g3/y3 in8 1 1 1 0 vin2 in9 hin2 in9 r2/v2 in9 b2/u2 in9 g2/y2 in9 0 0 0 1 vin1 in10 hin1 in10 r1/v1 in10 b1/u1 in10 g1/y1 in10 1 0 0 1 indefinite indefinite dc dc dc 0 1 0 1 indefinite indefinite dc dc dc 1 1 0 1 indefinite indefinite dc dc dc 0 0 1 1 indefinite indefinite dc dc dc 1 0 1 1 indefinite indefinite dc dc dc 0 1 1 1 indefinite indefinite dc *1 dc dc 1 1 1 1 hout1 out4 vout1 out4 g1/y1 out4 b1/u1 out4 r1/v1 out4 01/d1 01/d0 01/d2 01/d3
AN15865A 20 sdb00102aeb ? i 2 c bus conditions (continued) out5 signal select *2 *2 dc dc cv1 in1 0 0 0 0 *2 *2 dc dc cv2 in2 1 0 0 0 *2 *2 dc dc cv3 in3 0 1 0 0 *2 *2 v7/sc4 in4 u7/sy4 in4 y7/cv4 in4 1 1 0 0 *2 *2 v6/sc5 in5 u6/sy5 in5 y6/cv5 in5 0 0 1 0 *2 *2 v5/sc6 in6 u5/sy6 in6 y5/cv6 in6 1 0 1 0 *2 *2 v4/sc7 in7 u4/sy7 in7 y4/cv7 in7 0 1 1 0 *2 *2 r3/v3 in8 b3/u3 in8 g3/y3 in8 1 1 1 0 *2 *2 r2/v2 in9 b2/u2 in9 g2/y2 in9 0 0 0 1 *2 *2 r1/v1 in10 b1/u1 in10 g1/y1 in10 1 0 0 1 *2 *2 dc dc dc 0 1 0 1 *2 *2 dc dc dc 1 1 0 1 *2 *2 dc dc dc 0 0 1 1 *2 *2 dc dc dc 1 0 1 1 *2 *2 dc dc dc 0 1 1 1 *2 *2 dc *1 dc dc 1 1 1 1 hout2 out5 vout2 out5 g2/y2 out5 b2/u2 out5 r2/v2 out5 02/d1 012d0 02/d2 02/d3 note) *1 : 3.5 vdc are outputted at the time of mute mode *2 : it is based on a setup of sync distinction
AN15865A 21 sdb00102aeb ? i 2 c bus conditions (continued) status register continue am data (x + 1) data (x + 2) am data (x) am slave address (85 or 8d) s 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : no use 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : no use aspect ratio sa6 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : no use aspect ratio sa5 00 : 4:3 video signal 01 : 4:3 letter- box 10 : 16:9 video signal 11 : no use aspect ratio sa4 aspect ratio sa3 data0 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 out5 system status afc-lock 0 : unlock 1 : lock pin detect sb6 0 : open 1 : connect pin detect sb5 0 : open 1 : connect pin detect sb4 0 : open 1 : connect pin detect sb3 0 : open 1 : connect data1 0 signal detect 0 : no signal 1 : signal input australia format 0 : 1 152i 1 : 1 152i(letter) australia interlace 0 : except australia 1 : australia auto distinc. result sync fix 0 : continue 1 : fix auto distinc. result cvsydet 0 : sy 1 : cv macro vision detection (out5) 0 : normal signal 1 : macro vision signal sync status 0 : 2 value 1 : 3 value data2 d1 d0 d4 d3 d2 d6 d5 d7 note) the default data at the time of power-on is 0. note) am = ack from master r/w = 1 y the AN15865A selects slave address 85 or 8d(hex) according to the status of the slvadr pin. address 85(hex) will be selected with the slvadr pin grounded the the gnd side. address 8d(hex) will be selected with the pin grounded to the 5-v line.
AN15865A 22 sdb00102aeb ? i 2 c bus conditions (continued) description of registers 1. control register out1 signal select : selects the input in1 to in7 for out1(cv1, sy1, sc1) (including mute mode) out2 signal select : selects the input in1 to in7 for out2(cv2, sy2, sc2) (including mute mode) out3 signal select : selects the input in1 to in7 for out3(cv3, sy3, sc3) (including mute mode) out4 signal select : selects the input in1 to in10 for out4(g1/y1, b1/u1, r1/v1, hout1, vout1) out5 sync distinction : switches the sync identification afc circuit operating mode 0 = automatic identification (with priority ranking) (if input signal to both cv and sy, sy signal will be selected) 1 = uses cv or y input 2 = uses sy input 3 = free-run free-run priority : the priority of a free-run is changed 0 = fixed mode 1 = auto distinction will be started if a signal is inputted into a sync block while input signal is removed, return to free-run mode. (free-run priority only enabled when out5 sync distinction = free-run) out5 sync : selects h, v signal of hout2, vout2 whether independent h and v or afc h and v 0 = afc h and v 1 = independent h and v out5 signal select : selects the input in1 to in10 for out5(g2/y2, b2/u2, r2/v2, hout2, vout2) out4 matrix : selects the type of matrix conversion of out4 0 = through 1 = ccir protocol 2 = bta protocol 3 = convert gbr to yuv out5 matrix : selects the type of matrix conversion of out5 0 = through 1 = ccir protocol 2 = bta protocol 3 = convert gbr to yuv dummy sync mode control : selects the type of output sync format of out5 0 = 480i / 60 1 = 480p / 60 2 = 1080i / 60 3 = 720p / 60 4 = 576i / 50 5 = 576p / 50 6 = 1 080i / 50 7 = 720p / 50 hvout2 polarity : select the polarity of hout2 and vout2 at afc mode 0 = positive, sync level is high 1 = negative, sync level is low
AN15865A 23 sdb00102aeb ? i 2 c bus conditions (continued) cv1 gain : select the gain of out1(cv1) 0 = 0 db 1 = 6 db sy1/sc1 gain : select the gain of out1(sy1, sc1) 0 = 0 db 1 = 6 db cv2 gain : select the gain of out2(cv2) 0 = 0 db 1 = 6 db sy2/sc2 gain : select the gain of out2(sy2, sc2) 0 = 0 db 1 = 6 db cv3 gain : select the gain of out3(cv3) 0 = 0 db 1 = 6 db sy3/sc3 gain : select the gain of out3(sy3, sc3) 0 = 0 db 1 = 6 db out4 gain : select the gain of out4(g1/y1, b1/u1, r1/v1) 0 = 0 db 1 = 6 db out5 gain : select the gain of out5(g2/y2, b2/u2, r2/v2) 0 = 0 db 1 = 6 db out1 lpf : this switch selects lpf on/off of out1 0 = through 1 = lpf on out2 lpf : this switch selects lpf on/off of out2 0 = through 1 = lpf on out3 lpf : this switch selects lpf on/off of out3 0 = through 1 = lpf on out4 lpf : this switch selects lpf on/off of out4 0 = through 1 = lpf on out5 lpf : this switch selects lpf on/off of out5 0 = through 1 = lpf on out1 dcout : selects the dc level to out1(sc1) . this dc level corresponds to s2 standard. 0 = 0 v 1 = 1.9 v 2 = indefinite 3 = 4.5 v field monitor select : selects the field distinction signal in interlace mode, or the oscillation clock of built-in vco 0 = field1/field2 out (field1 : low field2 : high) 1 = clock monitor out input4 u/sy select : the mode changeover switch of an incoming signal 0 : sy input select 1 : u input select
AN15865A 24 sdb00102aeb ? i 2 c bus conditions (continued) input5 u/sy select : the mode changeover switch of an incoming signal 0 : sy input select 1 : u input select input6 u/sy select : the mode changeover switch of an incoming signal 0 : sy input select 1 : u input select input7 u/sy select : the mode changeover switch of an incoming signal 0 : sy input select 1 : u input select input8 br/uv select : the mode changeover switch of an incoming signal 0 : br input select 1 : uv input select input9 br/uv select : the mode changeover switch of an incoming signal 0 : br input select 1 : uv input select input10 br/uv select : the mode changeover switch of an incoming signal 0 : br input select 1 : uv input select australia free-run : set up, when you oscillate the free-run of the australia signal 0 = except australia 1 = australia mode 2. status register scart ident sa3 : return the control voltage of sa3(pin 51) 0 = less than 1 v 1 = 2 v or more to less than 3 v 2 = 4 v or more 3 = indefinite scart ident sa4 : return the control voltage of sa4(pin 55) 0 = less than 1v 1 = 2 v or more to less than 3 v 2 = 4 v or more 3 = indefinite scart ident sa5 : return the control voltage of sa5(pin 47) 0 = less than 1v 1 = 2 v or more to less than 3 v 2 = 4 v or more 3 = indefinite scart ident sa6 : return the control voltage of sa6(pin 59) 0 = less than 1v 1 = 2 v or more to less than 3 v 2 = 4 v or more 3 = indefinite pin detect sb3 : return the control voltage of sb3(pin 53) 0 = 5 v(open) 1 = 0 v(connected) pin detect sb4 : return the control voltage of sb4(pin 57) 0 = 5 v(open) 1 = 0 v(connected)
AN15865A 25 sdb00102aeb ? i 2 c bus conditions (continued) pin detect sb5 : return the control voltage of sb5(pin 45) 0 = 5 v(open) 1 = 0 v(connected) pin detect sb6 : return the control voltage of sb6(pin 61) 0 = 5 v(open) 1 = 0 v(connected) afc-lock : indicate the afc lock status in the sync separation 0 = unlocked 1 = locked out5 system status : return the input signal format after sync separated 0 = 480i / 60 4 = 576i / 50 1 = 480p / 60 5 = 576p / 50 2 = 1080i / 60 6 = 1080i / 50 3 = 720p / 60 7 = 720p / 50 sync status : return of identifying whether the input is ternary sync 0 = binary sync 1 = tri-level sync macro vision : indicate the whether to be a macro vision signal 0 = normal signal 1 = macro vision signal auto distinction result of cv/sy detection : the detection result is indicated on which sync shall have ridden between "cv" or "sy" 0 = sy 1 = cv auto distinction result of sync fixing situation : it indicates whether the detection result of auto distinction fixed 0 = under the check 1 = fixed australia interlace : it indicates whether the input signal is australia format 0 = except australia 1 = australia australia format : it indicates the type of australia format 0 = 1152i 1 = 1152i(litter) signal detect : it indicates whether there is input signal 0 = no signal 1 = signal input
AN15865A 26 sdb00102aeb ? test circuit diagram bus control vin6 v6/sc5 hin6 u6/sy5 sb5 y6/cv5 sa5 cv1 gnd1 cv2 sa3 sb3 cv3 u7/sy4 sa4 y7/cv4 sb4 v7/sc4 sa6 y5/cv6 sb6 u5/sy6 v5/sc6 hin5 sy1 dcout sc1 cv2/sy2 gnd sc2 gnd2 slvadr v cc3 g1/y1 sc3 cv3/sy3 gnd v cc2 cv1 hout1 vin5 y4/cv7 hin4 u4/sy7 vin4 v cc1 v4/sc7 hin3 b3/u3 vin3 r3/v3 v cc4 hin2 g2/y2 g3/y3 b2/u2 hin1 b1/u1 vin1 afc1 r1/v1 sync-out gnd4 g1/y1 sync-in r2/v2 sda scl field monitor r2/v2 vout2 hout2 b2/u2 gnd3 g2/y2 vsyncsepa r1/v1 vout1 b1/u1 vin2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 5 v 9 v 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 75 k ? 22 nf 0.47 f 0.47 f 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? 10 nf 4.7 k ? 4.7 f 10 f 10 k ? 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f0.47 f0.47 f0.47 f0.47 f0.47 f0.47 f0.47 f0.47 f hv signal generator signal generator 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? output 2 output 4 output 3 output 1 5 v 9 v 10 f 10 k ? 10 f 10 k ? 10 f 10 k ? output 5 input 10 input 4 input 5 input 7 input 8 input 1 input 2 input 6 input 9 input 3 3.3 v 10 f 10 k ? 10 f 10 k ?
AN15865A 27 sdb00102aeb ? technical data 1. circuit diagrams of the input/output part and pin function descriptions note) the characteristics listed below are reference values based on the ic design and are not guaranteed. g/y, b/u, r/v, u/sy, y/cv signal input pins. 2 5 7 9 44 46 48 50 52 54 56 60 62 66 68 72 74 76 78 80 independent h, v signal input pins. 1 6 8 41 43 63 65 67 69 73 75 79 description inner circuit pin no. v in pin 1, 8, 41, 65, 69, 75 h in pin 6, 43, 63, 67, 73, 79 g/y pin 5, 72, 78 b/u pin 7, 74, 80 r/y pin 2, 9, 76 u/sy pin 44, 56, 62, 68 y/cv pin 46, 48, 50, 52, 54, 60, 66 12k 3.7 v 4 v 90k 9 v 25 25 25 50 12k 34k 5 v 85k 60k 40k 75k 1k 200k 2 v
AN15865A 28 sdb00102aeb i 2 c bus clock input pin. 4 afc filter pin. 10 i 2 c bus data input pin. 3 description inner circuit pin no. afc1 pin 10 scl pin 4 sda pin 3 50 5 v 12k 50k 1.9 v 30k 90k 1.5k ack 50 5 v 12k 50k 1.9 v 30k 90k 1.5k 25 900 5 v 12k 9 v ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions note) the characteristics listed below are reference values based on the ic design and are not guaranteed.
AN15865A 29 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. sync signal output pin for sync separation. 12 sync signal input pin for sync separation. 13 5v system ground pin. 11 description inner circuit pin no. gnd4 pin 11 sync-out pin 12 sync-in pin 13 100 9 v 12k 100 12k 1.5v 5v 60 80 1.3 40 3
AN15865A 30 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. field change signal output pin. 15 v sync separation filter pin. 14 description inner circuit pin no. v sync sepa pin 14 field monitor pin 15 12 10 40 0.022 75k 17k 80k 12k 5 v 3.3 v 9 v 12k
AN15865A 31 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. independent h, v signal output pins 23 25 5 v system ground pin. 21 afc or independent h, v signal output pins. 17 19 g/y, b/u, r/v, cv/sy, sc signal output pins. 16 18 20 22 24 26 28 30 32 34 36 38 40 description inner circuit pin no. g/y pin 20, 26 b/u pin 18, 24 r/v pin 16, 22 cv/sy pin 30, 34, 38, 40 sc pin 28, 32, 36 100 9 v 12k 100 vout pin 17, 23 hout pin 19, 25 gnd3 pin 21 3.3 v 9 v 12k
AN15865A 32 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. pin to output dc voltage corresponding to s2, which overlaps the sc1 signal on output 1. the dc voltage varies with the setting in the control register. 37 29 9 v system ground pin. 31 35 33 5 v system power supply pin. x apply 5 v. 27 description inner circuit pin no. 05/d2 05/d1 dc value 0 0 1 1 0 1 0 1 0 v 1.9 v indefinite 4.5 v 5 v 200k 60k 2 v 40k 85k 34k 75k 12k slvadr pin 35 gnd pin 33 gnd2 pin 31 gnd pin 29 vcc3 pin 27 dcout pin 37 25 50 35k 12k circuit 12k 5 v
AN15865A 33 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. v/sc signal input pins. 42 58 64 70 pin status detection pins. pin opened : no signal. pin shorted : with signal. status data is transferred to the microcomputer in serial. 45 53 57 61 9 v system power supply pin. x apply 9 v. 39 description inner circuit pin no. vcc2 pin 39 12k 4 v 9 v 25 25 50 90k v/sc pin 42, 58, 64, 70 sb pin 45, 53, 57, 61 5 v 200k 60k 2 v 40k 85k 34k 75k 12k circuit 12k 9 v
AN15865A 34 sdb00102aeb ? technical data (continued) 1. circuit diagrams of the input/output part and pin function descriptions (continued) note) the characteristics listed below are reference values based on the ic design and are not guaranteed. 9 v system power supply pin. x apply 9 v. 71 5 v system ground pin. 49 5 v system power supply pin. x apply 5 v. 77 aspect ratio detection pins. 47 51 55 59 description inner circuit pin no. pin voltage 5.0 v to 4.0 v 3.0 v to 1.7 v 1.0 v to 0 v aspect ratio 16 : 9 letter-box 4 : 3 vcc1 pin 71 vcc4 pin 77 gnd1 pin 49 12k 34k 5 v 85k 29k 32k 24k 3.5 v 200k 39k 1.6 v 85k 85k sa pin 47, 51, 55, 59 circuit 12k 9 v circuit 12k 5 v
AN15865A 35 sdb00102aeb ? technical data (continued) 2. notes on video gain 1 v[p-p] 1 v[p-p] 0 db use 2 v[p-p] 6 db use input output 0 db / 6 db i 2 c control 0 db i 2 c control 2 v[p-p] 2 v[p-p] for 1 v[p-p] input signal, both 0 db and 6 db gain can be enabled. however, for 2 v[p-p] input signal, only 0 db gain is allowe d for normal operation. the gain of sy + sc can be controlled by control register sy/sc gain. sy/sc gain = 0 sy + sc = ?6 db sy/sc gain = 1 sy + sc = 0 db please note that the gain of sy + sc is not controlled by control resister cv gain. 0 db / 6 db i 2 c control sy + sc 0 db / 6 db sy sc 3 . other supplementary matters y the remedy of apl change please attach resistance of 1 m ? -3 m ? to each pin of cv and sy between opposite gnd by carrying out that it is hard to receive apl change. y how to output a synchronous separation output to hout2 to vout2 please choose "1" by test76(07/d6) and out5 sync(02/d4) in a control register, respectively.
AN15865A 36 sdb00102aeb ? usage notes 1. for use, voltages above 5.5 v should not be applied to the following pins. (pin no. 15, 17, 19, 23, 25) 2. pay enough attention to that following items when using the ic, otherwise the ic may break or give off smoke. y do not insert the ic in the reverse direction. 3. keep in mind the it may cause a latch-up by the following pins in the examination of the method of pulse current. pin number merit level (ma) 46 ?100 47 ?90 52 ?80 53 ?70 62 ?80 be careful not to impress the pulse current more than the above. the current level is describing the merit value of the pulse current which a latch-up does not generate. however, in all pins, a latch-up is not caused by the examination of the cv method. (200pf 200v) 4. purchase of panasonic i 2 c components conveys a license under the philips i 2 c patent right to use these components in an i 2 c systems, provided that the system conforms to the i 2 c standard specifications as defined by philips.
request for your special attention and precautions in using the technical information and semiconductors described in this material (1) an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. (2) the technical information described in this material is limited to showing representative characteris- tics and applied circuits examples of the products. it neither warrants non-infringement of intellec- tual property right or any other rights owned by our company or a third party, nor grants any license. (3) we are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) the products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instru- ments and household appliances). consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. ? any applications other than the standard applications intended. (5) the products and product specifications described in this material are subject to change without notice for modification and/or improvement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (6) when designing your equipment, comply with the guaranteed values, in particular those of maxi- mum rating, the range of operating power supply voltage, and heat radiation characteristics. other- wise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) when using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) this material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of matsushita electric industrial co., ltd. 2002 jul

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